1. Field of the Invention
The present invention relates to a semiconductor multi-port RAM mounted on an information processor.
2. Description of the Prior Art
FIG. 6 illustrates an example of a configuration of an information processor having a multi-port RAM.
An information processor 1 comprises a CPU 2 and a multi-port RAM 3. Multi-port RAM 3 has an interrupt circuit 4 for interrupting CPU 2, a memory control circuit 5, and a memory cell portion 6, i.e., a recording region. An address 9 for interrupt generation is an address in an allotted address region of multi-port RAM 3.
Multi-port RAM 3 has three ports, a port A, a port B, and a port C. Port A is connected to CPU 2, and ports B and C are connected to external information processors 8A and 8B, respectively. Memory control circuit 5 receives requests for access to multi-port RAM 3 from CFU 2 and external information processors 8A and 8B. The access results are then processed and executed by memory control circuits sequentially at a predetermined timing. Ports A, B and C are respectively provided with a data bus, an address bus, and an access requesting line (e.g. a line for a write request signal).
Interrupt circuit 4 is configured as shown in FIG. 7. Interrupt circuit 4 comprises decoding circuits 20 and 21 for decoding a specific address value, FFFF.sub.H input to ports B and C, and circuits 22 and 23 for decoding a writing in a specific address FFFF.sub.H, and an OR circuit 24. An output signal IRQ (DPRAM) of OR circuit 24 is imparted to CPU 2 shown in FIG. 6, as an interrupt signal. When a writing in the multi-port RAM is performed by means of port B or C, with write signals WR(B) or WR(C), respectively, and when the address to which the writing has been effected is a specific address a i.e., FFFF.sub.H, an interrupt is generated for CFU 2, and this address is, for instance, a final address 9 of RAM 6.
A description will now be given of the operation of information processor 1 shown in FIG. 6. As a method of generating an interrupt by the external information processors 8A and 8B at the time of writing to multi-port RAM 3, when an access signal WR of either of the external information processor 8A or 8B is input to information processor 1, information processor 1 generates an interrupt to CPU 2 if an address to which a writing is effected at the time of that writing operation is a specific address for generating an interrupt.
However, if an interrupt due to writing in multi-port RAM 6 is effected with respect to only one specific address, e.g., "FFFF.sub.H ", there arises a need to conduct address adjustment in such as data transmission from the outside. As a result, it has been impossible to effect complicated processing involved in the processing of a generated interrupt, so that the information processing capability has been restricted.